1. Field of the Invention
The present invention relates to a semiconductor device used with a high frequency band, and in particular relates to a semiconductor device of planar structure which reduces channel resistance using a semiconducting material with a high electric field which reaches saturation electron velocity, such as GaN.
2. Description of the Related Art
A semiconductor device used with a high frequency band, for example, a microwave power amplifying device, is composed of active elements, such as a field effect type transistor, passive elements, such as resistance and a capacitor, and circuit elements, such as a microstrip lines for transmitting a high frequency signal.
These circuit elements are formed, for example on a semi-insulating substrate. An electrode for grounding is formed on a backside of the semi-insulating substrate. And, when grounding the circuit element, the electrode for grounding formed on the backside of the semi-insulating substrate is electrically connected with the circuit element provided on the semi-insulating substrate through a VIA hole (via hole) which passes through the semi-insulating substrate, for example (for example, refer to Patent Document 1 and Patent Documents 2).
A semiconductor device provided with a plurality of active areas selectively formed on a semi insulating semiconductor substrate is already disclosed (for example, refer to Patent Document 3).
A semiconductor device which expands a thermal diffusion path and reduces thermal resistance by dividing an active layer region by an isolation region formed in the direction perpendicular to a gate electrode finger is already disclosed (for example, refer to Patent Document 4).
A high frequency high power semiconductor device provided with a thermal spacer which divides at least one unit cell into a first active area (active portion) and a second active area (active portion), which the first active area and the second active area which are formed selectively are offset and are placed for thermal diffusion is already disclosed (for example, refer to Patent Document 5).
FIG. 1 shows a semiconductor device according to a conventional example, FIG. 1A shows its schematic section structure chart, and FIG. 1B shows its schematic plane pattern configuration diagram.
As shown in FIG. 1, the semiconductor device according to the conventional example, for example, includes: a substrate 10; a GaN epitaxial growth layer 12 placed on the substrate 10; an AlGaN layer 18 placed on the GaN epitaxial growth layer 12; a source electrode 20 and a drain electrode 22 which are placed on the AlGaN layer 18; a gate electrode 24 placed at a recess part on the AlGaN layer 18; and a non-active area (isolation region) 14 formed on a part of the AlGaN layer 18 and the GaN epitaxial growth layer 12. A 2DEG (Two Dimensional Electron Gas) layer 16 is formed on an interface with the AlGaN layer 18 on the GaN epitaxial growth layer 12. The semiconductor device shown in FIG. 1 is equivalent to HEMT (High Electron Mobility Transistor).
In the semiconductor device according to the conventional example, as shown in FIG. 1, in order to reduce a value of resistance of a source resistance Rs which is a channel resistance between the source electrode 20 and the gate electrode 24, the thickness of the AlGaN layer 18 directly underneath of the source electrode 20 is set up thicker than the thickness of the AlGaN layer 18 directly underneath of the gate electrode 24. On the other hand, in order to improve the controllability of gate voltage applied to the gate electrode 24, the thickness of the AlGaN layer 18 directly underneath of the gate electrode 24 is set up thinner.
By reducing the source resistance Rs, the ON resistance can be reduced and the rising characteristics of the drain current ID can be improved in drain current ID versus drain-source voltage VDS characteristics.
In the semiconductor device according to the conventional example, as shown in FIG. 1, width WA1 of an active area 30 (AA1) between gate and source placed between the source electrode 20 and the gate electrode 24 and width WA2 of an active area 32 (AA2) between gate and drain placed between the gate electrode 24 and the drain electrode 22 are designed to be equal.
FIG. 2 shows a schematic plane pattern configuration of a semiconductor device according to a conventional example, FIG. 2A shows a schematic plane pattern configuration diagram of a unit element, FIG. 2B shows a schematic plane pattern configuration diagram of the semiconductor device which extends channel width of the unit element, and FIG. 2C shows a schematic plane pattern configuration diagram of the semiconductor device which turned up the semiconductor device shown in FIG. 2B in the source/drain direction of centering on a drain electrode.
In the semiconductor device according to the conventional example, also in the extended device structure as shown in FIG. 2A to FIG. 2C, as well as in FIG. 1, width of an active area 30 (AA1) between gate and source placed between a source electrode 20 and a gate electrode 24 and width of an active area 32 (AA2) between gate and drain placed between the gate electrode 24 and a drain electrode 22 are designed to be equal.
Moreover, FIG. 3 shows a schematic plane pattern configuration of a semiconductor device according to a conventional example, FIG. 3A shows an enlarged drawing of a part of reference numeral A of FIG. 3B, and FIG. 3B shows an overall schematic plane pattern configuration diagram.
As shown in FIG. 3, the overall schematic plane pattern configuration of the semiconductor device according to the conventional example includes: a substrate 100; a gate electrode 24, a source electrode 20, and a drain electrode 22 which are placed on a first surface of the substrate 100 and have a plurality of fingers, respectively; a gate terminal electrode 240, a source terminal electrode 200, and a drain terminal electrode 220 which are placed on the first surface of the substrate 100, and make bundles of a plurality of fingers and are formed, respectively every the gate electrode 24, the source electrode 20, and the drain electrode 22; an active area 30 between gate and source placed between the gate electrode 24 and the source electrode 20; an active area 32 between gate and drain placed between the gate electrode 24 and the drain electrode 22; and a VIA hole 260 connected to the source terminal electrode 200, wherein width of the active area 30 between gate and source is equal to width of the active area 32 between gate and drain.
In a configuration example of FIG. 3, as for the size of each part, for example, cell width W1 is about 120 micrometers, W2 is about 80 micrometers, cell length W3 is about 100 micrometers, W4 is about 120 micrometers, and gate width WG is about 2.4 mm (=100 micrometer×6×4 cells) as a whole.
In the example of FIG. 3, in the source terminal electrodes 200, the VIA holes 260 are formed from a backside of the substrate 100, and a ground conductor is formed on the backside of the substrate 100. And, when grounding the circuit element, the circuit element provided on the substrate 100 and the ground conductor formed on the backside of the substrate 100 are electrically connected through the VIA holes 260 which pass through the substrate 100.
In addition, the gate terminal electrodes 240 are connected to surrounding circuit elements by bonding wires etc., and the drain terminal electrode 220 is also connected to surrounding circuit elements by bonding wires etc.
In the conventional semiconductor device, since an electric field of the active area 30 placed between the source electrode 20 and the gate electrode 24 is lower than an electric field of the active area 32 placed between the gate electrode 24 and the drain electrode 22, the value of electron velocity in the active area 30 placed between the source electrode 20 and the gate electrode 24 is low. Since the value of the electron velocity is low, the value of channel resistance is increased, and as the result, high frequency characteristics are degraded.    Patent Document 1:    Japanese Patent Application Laying-Open Publication No. H02-288409    Patent Document 2:    Japanese Patent Application Laying-Open Publication No. 2001-28425    Patent Document 3:    Japanese Patent Application Laying-Open Publication No. S57-160148 (Pages 2 to 3, and FIG. 5)    Patent Document 4:    Japanese Patent Application Laying-Open Publication No. H08-213409 (Page 3 and FIG. 1)    Patent Document 5:    U.S. Patent Publication No. 7,135,747 (Page 6 and FIG. 2)